In the electronics industry there is a consistent trend to increase the number of devices that can be formed on a semiconductor wafer. This requires that extremely small line widths be photolithographically printed on the wafer. However, most photolithographic techniques are limited by the degree of flatness of the wafer surface for the depth of focus of projection printers cannot be adjusted to compensate for surface variation which restricts the resolution of the fine line patterns.
The last step in most semiconductor fabrication processes, prior to forming devices on a wafer, is to polish the wafer to as high a degree of flatness as possible. One well known technique is to place the wafer between a stainless steel, polyurethane coated, holder and a polishing pad. The wafer is tightly held by the polyurethane coating while the holder and the pad are rotated in same direction to polish the wafer. This technique results in variations of surface flatness of approximately eight microns. Such variations result in decreased yields of acceptable devices as the number of devices per unit area increases.
One technique that overcomes the foregoing problem is described in U.S. Pat. No. 4,256,535 to E. L. Banks, which is assigned to the instant assignee and is incorporated by reference herein. That patent teaches the placing of a drop of liquid on a flat, non-porous substrate and positioning a wafer thereon. The wafer is then polished with a rotating polishing pad while the wafer is permitted free floating, rotating motion on a thin layer of water during the polishing. Such a technique has been found to be most effective when polishing at low pressures (e.g., 3 psi or less), however, when polishing wafers under higher pressures the wafer is forced through the thin liquid layer resulting in breakage and/or nonuniform flatness during the polishing operation. However, polishing wafers at such higher pressures is most desirable in that the time required to polish a wafer is substantially reduced.
Accordingly, there is a need for a high pressure semiconductor wafer polishing technique that can provide acceptable flatness variations of the wafer while substantially eliminating breakage.